This relates generally to integrated circuits (i.e. chips) that selectively provide a variety of different features.
Various integrated circuits may have many different selectable features. For example, a system on a chip may have a wide variety of capabilities. Different interested parties may have different interests in various ones of these features. For example, a chip manufacturer may need to be able to manufacture the chips, test the chips and perform failure analysis on customer returns. An original equipment manufacturer may need to do failure analysis. Thus, in different cases, different parties may need different levels of access to debug mechanisms.
Currently, a password may be provided to unlock access to the Joint Test Action Group (JTAG) interface. Then additional fuses may be provided to protect each debug feature once the JTAG access is granted. Examples of this include boundary scan (BSCAN), memory built-in self-test (mBIST), VISA, and OMAR debugging technologies.